The present disclosure relates generally to semiconductor device manufacturing techniques and, more particularly, to the elimination of puddles in semiconductor device wiring due to bubble formation in optical planarization layers.
In the manufacture of semiconductor devices, processing operations generally fall under two main categories. Specifically, “front end of the line” (FEOL) processing is dedicated to the formation of active devices such as transistors in the body or substrate of the semiconductor device, whereas “back end of the line” (BEOL) processing involves the formation of metal interconnect structures, which connect all the active devices with each other as well as with the external world. The FEOL consists of a repeated sequence of steps that modifies the electrical properties of part of a wafer surface and forms new material(s) above selected regions. Once all active components are created, the upper phase of manufacturing (BEOL) begins. During the BEOL, metal interconnects are created to establish the connection pattern of the semiconductor device.
As feature sizes continue to scale down in semiconductor industry, the fabrication process of integrated circuit devices becomes more and more complex. Advanced semiconductor designs typically incorporate multilayer structures. For example, during the process of formation of a metal interconnect, usually a hardmask layer, a planarization layer and an antireflective coating (ARC) layer are sequentially formed on a substrate with a dielectric layer thereon. A photoresist layer is then formed on top of the ARC layer. The definition of the pattern is formed by photolithography on the photoresist layer. The resist pattern is transferred to the ARC layer via an etch process using the photoresist film as a mask. Similarly, the ARC pattern is transferred sequentially through all other underlying layers, and finally, a pattern is formed on the substrate.